1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
In methods for manufacturing a semiconductor device by using a plurality of semiconductor chips with different functions, the semiconductor device is manufactured by cutting out the semiconductor chips with different functions from a plurality of wafers obtained through different processes and using them in any desired combinations. Thus, in general, these methods are superior to methods for manufacturing a semiconductor device by integrating all the desired functions onto one chip in terms of manufacturing cost.
One of the above-described methods for manufacturing a semiconductor device by using a plurality of semiconductor chips with different functions is called a “chip-on-chip method”, in which a plurality of semiconductor chips are stacked vertically and connected to each other via bumps.
FIG. 9 is a cross-sectional view showing one example of a semiconductor device manufactured by a conventional chip-on-chip method. As shown in FIG. 9, in the semiconductor device manufactured by the conventional chip-on-chip method, a second semiconductor chip 101b and a first semiconductor chip 101a are stacked on the substrate 103 in this order.
Electrical connection between the first semiconductor chip 101a as an uppermost semiconductor chip and the second semiconductor chip 101b provided below the first semiconductor chip 101a is achieved by connecting electrode pads (not shown) provided on a surface on which a circuit is formed (hereinafter, referred to simply as a “circuit surface”) of the first semiconductor chip 101a to electrode pads (not shown) provided on a circuit surface of the second semiconductor chip 101b via bumps 102. These bumps 102 form a space between the first semiconductor chip 101a and the second semiconductor chip 101b, and the space is filled with an underfill material 104.
The second semiconductor chip 101b is bonded to the substrate 103 with an adhesive (a die bonding material) 105. Electrical connection between the second semiconductor chip 101b and the substrate 103 is achieved by connecting bonding pads (not shown) provided on the circuit surface of the second semiconductor chip 101b to electrode pads (not shown) provided on the substrate 103 via wires 106.
On the bottom of the substrate 103, lands 103a serving as terminals for connection to an external component or device are formed. The first semiconductor chip 101a and the second semiconductor chip 101b on the substrate 103 are encapsulated in an encapsulation resin layer 107 formed of encapsulation resin.
As shown in FIG. 9, according to the chip-on-chip method, a plurality of semiconductor chips can be electrically connected to each other via bumps. Thus, the first semiconductor chip 101a and the second semiconductor chip 101b may be manufactured by separate processes. For example, by manufacturing the first semiconductor chip 101a through a process designed specifically for the manufacture of DRAM and the second semiconductor chip 101b through a process designed specifically for the manufacture of CMOS and then connecting the first semiconductor chip 101a and the second semiconductor chip 101b by flip chip bonding, a high-performance semiconductor device with DRAM can be manufactured at a low cost without performing a process integrating a process for manufacturing DRAM with a process for manufacturing CMOS.
Furthermore, in the semiconductor device shown in FIG. 9, the circuit thereof is constituted by the two separate elements, i.e., the first semiconductor chip 101a and the second semiconductor chip 101b. This allows the interconnection length to be shortened, thereby improving the manufacturing yield. In addition, the semiconductor device shown in FIG. 9 also is advantageous in that, since the semiconductor chips are stacked vertically, it requires a smaller area, thus achieving miniaturization of the semiconductor device.
Next, processes for manufacturing a semiconductor device according to a conventional chip-on chip method will be described with reference to FIGS. 10A to 10F. FIGS. 10A to 10F are cross-sectional views, each illustrating one part of the method for manufacturing the semiconductor device shown in FIG. 9. The parts illustrated from FIG. 10A through FIG. 10F are a series of major parts of the process. Specifically, FIG. 10A is a die bonding process, FIG. 10B is a flip chip bonding process, FIG. 10C is an underfill process, FIG. 10D is a wire bonding process, and FIG. 10E is an encapsulating process.
First, as shown in FIG. 10A, the second semiconductor chip 101b is disposed on the substrate 103 via the adhesive 105. The second semiconductor chip 101b is disposed with the circuit surface thereof having the electrode pads (not shown) facing up (i.e., facing toward the direction opposite to the substrate 103). Thereafter, the adhesive 105 is cured with heat. The heating may be performed with either an in-line system or a batch processing with an oven. Thus, the second semiconductor chip 101b is fixed on the substrate 103.
Next, as shown in FIG. 10B, the first semiconductor chip 101a is mounted on the second semiconductor chip 101b by flip chip bonding with the circuit surface thereof facing down (i.e., facing toward the substrate 103). It is to be noted here that the bumps 102 are formed on the electrode pads (not shown) provided on the circuit surface of the first semiconductor chip 101a. Accordingly, the electrode pads (not shown) of the first semiconductor chip 101a and the electrode pads (not shown) of the second semiconductor chip 101b are electrically connected to each other via the bumps 102.
Then, as shown in FIG. 10C, the underfill material 104 made of liquid resin is filled into the space formed between the first semiconductor chip 101a and the second semiconductor chip 101b by the bumps 102. Thus, the first semiconductor chip 101a and the second semiconductor chip 101b are bonded with the underfill material 104 and fixed to each other.
After that, as shown in FIG. 10D, the bonding pads (not shown) of the second semiconductor chip 101b are electrically connected to the electrode pads (not shown) of the substrate 103 via the wires 106.
Subsequently, as shown in FIG. 10E, the stacked product including the substrate 103, the second semiconductor chip 101b, and the first semiconductor chip 101a, obtained by the processes illustrated from FIGS. 10A through 10D, is placed inside a mold 110 that has been heated to a molding temperature.
The mold 110 is formed with an upper half 110a having a recess 108a and a lower half 110b having a recess 108b. The recess 108a is formed so that it can accommodate the second semiconductor chip 101b and the first semiconductor chip 101a, and the recess 108b is formed so that the substrate 103 fits therein. These recesses 108a and 108b define the cavity 108 inside the mold 110.
Next, melted encapsulation resin is transferred into a space defined by the inner wall of the recess 108a of the upper half 110a and the stacked product obtained by the processes illustrated from FIGS. 10A through 10D. Thus, the space is filled with the encapsulation resin. This state is maintained for 1 to 2 minutes so that the encapsulation resin is cured to form the encapsulation resin layer 107.
Then, as shown in FIG. 10F, the stacked product including the substrate 103, the second semiconductor chip 101b, and the first semiconductor chip 101a is taken out from the mold 110, and excess resin is removed from the encapsulation resin layer 107. Thus, the semiconductor device as shown in FIG. 9 is completed.
By the way, when the semiconductor device with such a large scale is operated at high speed, an increase in power consumption is inevitable, which results in increased heat generation. Although the chip-on-chip method is suitable for the manufacture of a high-performance semiconductor device with a large scale as described above, a semiconductor device manufactured by this method has a problem in that the heat dissipation characteristics thereof are not very good because a plurality of stacked semiconductor chips are encapsulated in encapsulation resin. Thus, when such a semiconductor device is used in electronic equipment such as a cellular phone or the like, malfunction and/or fault may be caused by the heat generated by the circuit.
In view of the above-described problem, JP 2001-57404 A discloses improving heat dissipation characteristics of a semiconductor device manufactured by the chip-on-chip method by grinding the upper surface of the encapsulation resin layer so that the upper surface of the uppermost semiconductor chip is exposed.
One example of such a semiconductor device is shown in FIG. 11. FIG. 11 is a cross-sectional view showing another example of a semiconductor device manufactured by a conventional chip-on-chip method. In FIG. 11, the same components as those in FIG. 9 are indicated with the same reference numerals.
The semiconductor device shown in FIG. 11 is obtained by grinding the encapsulation resin layer 107 covering the upper surface (the surface opposite to the circuit surface) of the first semiconductor chip 101a until the upper surface of the first semiconductor chip 101a is exposed. The upper surface of the first semiconductor chip 101a and the upper surface of the encapsulation resin layer 107 surrounding it are coplanar.
Furthermore, JP 2001-267470 A discloses improving the heat dissipation characteristics of the semiconductor device by attaching a heat sink to the surface of the uppermost semiconductor chip exposed from the encapsulation resin layer.
However, according to the techniques disclosed in JP 2001-57404 A and JP 2001-267470 A, a process of grinding the semiconductor device must be performed after the encapsulating process (FIG. 10E), which reduces the productivity and production efficiency. Also, the environmental impact of the debris produced during the grinding process cannot be disregard.
On the other hand, in recent years, in the field of electronic equipment such as a cellular phone or the like, there has been a demand for further reduction in the size and weight of such equipment as well as further expansion of their functions. In order to meet this recent demand, the packaging of circuit components is becoming denser and denser, thereby increasing the power consumption of such equipment. Thus, improving the heat dissipation characteristics is important in order to improve the reliability of the electronic equipment such as a cellular phone or the like. In particular, since some of the processors to be used in a cellular phone consume several watts of power, it is extremely important to improve the heat dissipation characteristics of the electronic equipment employing such processors.